The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a body providing a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A fin-type field-effect transistor may include a fin consisting of a body of semiconductor material, a gate structure that wraps about the fin, and heavily-doped source/drain regions spaced along the fin and arranged on opposite sides of the gate structure.
Gate structures may be initially formed as linear features that extend longitudinally across fins of fin-type field-effect transistors that are associated with different active device regions. After forming the gate structures, a masked etching process may be used to form cuts that divide the gate structures into sections that are associated with one active device region and sections that are associated with another active device region. The sections of the gate structures associated with the different active device regions are disconnected from each other in the final construction of the fin-type field-effect transistors in the different active device regions.
As fin pitch scales downward, providing a precision gate cut at locations between different device regions presents challenges with respect to process margin. Gate cuts at small dimensions may be incompletely formed, which may result in sections of the gate structures that are not fully disconnected. To resolve this issue, the etching process forming the gate cuts may be extended to provide an over-etch. However, the over-etch may unwantedly increase the dimensions of the gate cuts such that, among other effects, the gate contacts may land in part on the dielectric material filling the gate cuts.
Improved structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor are needed.